EEE U111 · Electrical Sciences · Module 3 · Lectures 9–12

Transients: First- & Second-Order Circuits

Bobrow & Gupta (Asian ed.) §3.2–3.5: what a circuit does in the moments after a switch moves. First-order RC and RL circuits, then second-order RLC; natural and forced response.

Start here — facts, not pep talk

Half of this module is new to the whole lecture hall. Classmates with a JEE background will have met the single RC or RL charging curve. None of them did second-order RLC circuits at school, where you have to find the constants from i(0⁺) and di/dt(0⁺). That part starts from zero for everybody.

The module is also highly routine. Every problem runs the same three snapshots (just before, just after, long after the switch) and then one of four solution shapes. In the four past mid-sem papers in our files, transients carried 20–40 of the 90 marks each time. It is the most mechanical big block in the course, so practice converts straight into marks.

The maths you need is short: e^x and ln, the quadratic formula, and differentiating e^st. It is all in the kit below.

First time through? Start with the first-time lesson. It covers the same scope, taught slowly with the intuition first. Then come back here to revise and to work through the examples.

1 · The game plan: three snapshots

A transient is the circuit's journey from one DC steady state to another after a switch moves. The one physical fact that controls everything is this: stored energy cannot change in zero time. In circuit terms, two quantities are continuous across the switching instant:

v_C(0⁺) = v_C(0⁻) i_L(0⁺) = i_L(0⁻)

Why: a jump in v_C would need i = C dv/dt = ∞, and a jump in i_L would need v = L di/dt = ∞. Everything else may jump: resistor currents, the capacitor's current, the inductor's voltage. And at DC steady state nothing changes, so every derivative is zero: i_C = C·0 = 0 (the capacitor acts as an open circuit) and v_L = L·0 = 0 (the inductor acts as a short).

Snapshot	Circuit to draw	What you get from it
t = 0⁻ (old steady state)	Old switch position; C → open, L → short	Only v_C(0⁻) and i_L(0⁻). Nothing else carries over.
t = 0⁺ (the instant after)	New switch position; C → voltage source v_C(0⁺), L → current source i_L(0⁺)	Any other initial value, plus the initial slopes di_L/dt = v_L/L, dv_C/dt = i_C/C
t → ∞ (new steady state)	New switch position; C → open, L → short	The final (forced) values

After the snapshots, one more number (or pair of numbers) gives the speed of the journey: τ for a first-order circuit, the roots s₁, s₂ for a second-order one.

2 · First-order circuits: one formula §3.2–3.5

Intuition. One storage element (one C or one L); everything else is resistors and sources. Thevenin (Module 2) squeezes that "everything else" into V_th in series with R_th. For a capacitor that gives C dv/dt = (V_th − v)/R_th: the capacitor charges at a rate proportional to how far it still has to go. Fast when far from the target, slower and slower as it closes in. That behaviour is exactly an exponential approach.

Formal statement. For any voltage or current x in a first-order circuit, for t ≥ 0:

x(t) = x(∞) + [x(0⁺) − x(∞)] e^−t/τ, τ = R_thC or τ = LR_th

Here R_th is the resistance seen by the storage element in the new (t > 0) circuit: independent sources killed (V → short, I → open), dependent sources left on. With a dependent source present, use a test source: remove the C or L, push a test current I into its terminals, compute the terminal voltage V, and take R_th = V/I. The other route is V_oc/I_sc. Every quantity in the circuit shares the same τ, but each one needs its own x(0⁺) and x(∞).

Every first-order response is this one curve, rescaled. The dashed tangent shows the starting slope: if the circuit kept its initial rate, it would arrive in exactly one τ.

Unpack: where 63% and 99% come from

At t = τ the remaining gap is e⁻¹ ≈ 0.368 of the original, so 63.2% of the journey is done. At 5τ the gap is e⁻⁵ ≈ 0.0067, under 1%. That is why "a long time" in a question means "many τ", and why you may treat the circuit as settled.

Worked example 1RC with a two-position switch, and "when does it cross zero?"

Worked example 1. The blade has sat on A for a long time; at t = 0 it flips to B. Note the 6 V source's + is at the bottom, so it pulls the capacitor node negative.

Find v(t) for t ≥ 0, and the time at which v = 0.

0⁻: blade on A, C open, so the 3 kΩ and 6 kΩ form a divider: v(0⁻) = 12 × 63 + 6 = 8 V.
0⁺: v(0⁺) = 8 V (capacitor voltage can't jump). The 2 kΩ current does jump: from 0 (it was disconnected) to (8 − (−6))/2 k = 7 mA, flowing from the capacitor node toward the 6 V source.
∞: blade on B, C open, divider again, with the source's sign: v(∞) = −6 × 62 + 6 = −4.5 V.
τ: kill the 6 V source (short) and look in from the capacitor. You see 2 kΩ ∥ 6 kΩ = 1.5 kΩ. The 3 kΩ is out of the circuit, because the blade has left A. τ = 1.5 kΩ × 50 µF = 75 ms.
Assemble: v(t) = −4.5 + (8 − (−4.5))e^−t/0.075 = −4.5 + 12.5 e^−t/0.075 V (t in seconds).
Zero crossing: set 12.5 e^−t/τ = 4.5, so t₁ = τ ln(12.5/4.5) = 0.075 × 1.0217 = 76.6 ms. Check a point: v(100 ms) = −4.5 + 12.5e^−1.333 = −1.21 V. It has crossed zero, as it should have.
Unpack: getting t out of the exponent

Divide first: e^−t/τ = 4.5/12.5 = 0.36. Take ln of both sides: −t/τ = ln 0.36 = −1.0217. Multiply by −τ. Flipping the fraction (ln(12.5/4.5)) is the same thing without the minus signs. See the kit.

Worked example 1, computed. The curve heads for −4.5 V from the first instant; it crosses zero just after one τ (75 ms).

Worked example 2RL with a dependent source: τ needs a test source

Worked example 2. The diamond is a current-controlled voltage source: its voltage is 2 volts per amp of i_x, the current down the 6 Ω.

The switch has been open for a long time and closes at t = 0. Find i(t), the inductor current.

0⁻ → 0⁺: no source has been connected, so i(0⁻) = 0 = i(0⁺).
∞: L is a short, so the terminal below the diamond sits at 0 V. KVL through the diamond: v_a − 2i_x = 0, with i_x = v_a/6. So v_a(1 − 13) = 0, giving v_a = 0. The 6 Ω carries nothing, and all of the 4 Ω current reaches L: i(∞) = 24/4 = 6 A.
R_th by test source: kill the 24 V (short), which leaves the 4 Ω going to ground. Remove L and push a test current I up into its terminal. It passes through the diamond into node a, then splits into the 4 Ω and 6 Ω: v_a = I(4 ∥ 6) = 2.4I, i_x = 0.4I. Terminal voltage: V = v_a − 2i_x = 2.4I − 0.8I = 1.6I, so R_th = 1.6 Ω.
Unpack: the sign through the diamond

The diamond's + is on the node-a side, so node a sits 2i_x above the terminal below it: v_a − V = 2i_x. It is the same rule as for any voltage source (Module 1). The only difference is that its value is a formula instead of a number.
Cross-check with V_oc/I_sc: with L removed (open), v_a = 24 × 6/10 = 14.4 V, i_x = 2.4 A, so V_oc = 14.4 − 4.8 = 9.6 V. I_sc = 6 A (step 2). 9.6/6 = 1.6 Ω ✓. Killing the diamond would have given 4 ∥ 6 = 2.4 Ω, which is wrong.
Assemble: τ = L/R_th = 0.5/1.6 = 0.3125 s, so i(t) = 6(1 − e^−3.2t) A.
Sanity check on the slope: at 0⁺ the inductor, carrying 0 A, looks like an open circuit, so v_L(0⁺) = V_oc = 9.6 V and di/dt(0⁺) = 9.6/0.5 = 19.2 A/s. The formula gives 6 × 3.2 = 19.2 ✓.

Worked example 3Two switching events: the clock restarts

Worked example 3. S₂ sits in a bypass across the 4 Ω: when it closes, the 4 Ω is shorted out of the circuit.

Both switches start open with no current flowing. S₁ closes at t = 0 and S₂ at t = 0.5 s. Find i(t), and its value at 0.25 s and at 1 s.

Phase 1, 0 ≤ t < 0.5 s: the loop has 2 + 4 = 6 Ω. i(0⁺) = 0, i(∞) = 12/6 = 2 A, τ₁ = 1/6 s. So i = 2(1 − e^−6t) and i(0.25) = 2(1 − e^−1.5) = 1.554 A.
Hand-over at 0.5 s: i(0.5) = 2(1 − e⁻³) = 1.900 A. The inductor current can't jump at the second switching either, so this becomes phase 2's initial value.
Phase 2, t ≥ 0.5 s: S₂ shorts the 4 Ω, so R = 2 Ω, i(∞) = 6 A, τ₂ = 1/2 = 0.5 s.
Assemble with a shifted clock: i(t) = 6 + (1.900 − 6)e^{−(t−0.5)/0.5} = 6 − 4.100 e^{−2(t−0.5)} A. Writing e^−2t without the shift is the standard mark-loser: at t = 0.5 the bracket must be zero, so that the exponential equals 1.
Evaluate: i(1) = 6 − 4.100e⁻¹ = 4.492 A.

Worked example 3, computed. A kink, not a jump: the current is continuous at 0.5 s, only its target and its τ change.

3 · Two numbers exams love: "how long until…" and "how much energy"

Time to reach a target. Solve x(t) = x_target for t. It always comes out as

t = τ ln x(0⁺) − x(∞)x_target − x(∞)

That is the ratio of "gap at the start" to "gap at the target". Worked example 1 step 6 is this formula.

Energy. A capacitor discharging from V₀ to zero releases all of ½CV₀². Resistors in series carry the same current, so they share that energy in proportion to R. If a question insists on an integral: ∫₀^∞ I₀² e^−2t/τR dt = I₀²Rτ/2. The exponent doubles because the current is squared.

Worked example 4Discharge: time to 10 V, and the 3 kΩ's share of the energy

Worked example 4. One loop: the charged capacitor dumps its energy into 2 kΩ + 3 kΩ in series.

τ and the start: τ = (2 k + 3 k)(20 µF) = 0.1 s, and v(t) = 50e^−10t V. The current jumps from 0 to i(0⁺) = 50/5 k = 10 mA as the switch closes.
Time to 10 V: e^−10t = 10/50 = 0.2, so t = 0.1 ln 5 = 0.161 s.
Energy, by sharing: total ½ × 20 µF × 50² = 25 mJ. The 3 kΩ takes 3/5 of it: 15 mJ.
Energy, by integral (check): ∫₀^∞(0.01)²e^−20t × 3000 dt = 0.3 × 120 = 0.015 J ✓.
Unpack: the integral of a decaying exponential

∫₀^∞e^−ktdt = [−e^−kt/k]₀^∞ = 0 − (−1/k) = 1/k. Here k = 20, because squaring e^−10t gives e^−20t.

4 · Initial conditions: i(0⁺), di/dt(0⁺), d²i/dt²(0⁺)

Intuition. At the instant 0⁺, every capacitor behaves like a battery of voltage v_C(0⁺) and every inductor like a current source i_L(0⁺). What is left is a plain resistive circuit, so Module 2 finds any voltage or current in it. Slopes come from the element laws read backwards: di_L/dt = v_L/L and dv_C/dt = i_C/C. For a second derivative, differentiate the KVL/KCL equation you already wrote and substitute the first-derivative values.

Worked example 5Three initial values from one circuit

Worked example 5. Position 1 for a long time; at t = 0 the blade moves to 2, which replaces the source by a plain wire.

Find i, di/dt and d²i/dt² at t = 0⁺.

0⁻: L is a short and C is open, so the loop is 12 V, 2 Ω, 4 Ω: i(0⁻) = 12/6 = 2 A, and v(0⁻) = 4 × 2 = 8 V. The capacitor sits across the 4 Ω.
0⁺: i(0⁺) = 2 A and v(0⁺) = 8 V. With the blade on 2, the left end of the 2 Ω is at ground (0 V).
KVL for the inductor: current i flows from ground through the 2 Ω toward L, dropping 2i, so the inductor's left end is at −2i. Its right end is at v. So L di/dt = −2i − v. At 0⁺: di/dt = (−4 − 8)/1 = −12 A/s.
KCL at the capacitor node: C dv/dt = i − v/4. At 0⁺: dv/dt = (2 − 2)/0.25 = 0.
Differentiate step 3's equation: L d²i/dt² = −2 di/dt − dv/dt. At 0⁺: d²i/dt² = −2(−12) − 0 = 24 A/s².

A numerical solution of the circuit's equations reproduces −12 A/s and 24 A/s² from the curve itself.

5 · Second-order circuits §3.2–3.5

Intuition. With both an L and a C, energy can slosh back and forth between them (electric field ↔ magnetic field) while R drains it. Too much draining gives a sluggish return with no swing (overdamped). Too little gives ringing that dies away (underdamped). The boundary case, critically damped, is the fastest return without overshoot. One number compares the draining with the sloshing: α against ω₀.

Formal statement. The natural response satisfies the characteristic equation

s² + 2αs + ω₀² = 0, s₁,₂ = −α ± √(α² − ω₀²), ω₀ = 1√(LC)

	Series RLC	Parallel RLC
α (s⁻¹)	R/(2L)	1/(2RC)
Where it comes from	KVL: Ri + L di/dt + v_C = 0, with i = C dv_C/dt	KCL: v/R + i_L + C dv/dt = 0, with v = L di_L/dt
Big R means…	more damping	less damping (a big parallel R hardly drains anything)

Case	Test	Roots	Natural response
Overdamped	α > ω₀	two real, negative	A₁e^s₁t + A₂e^s₂t
Critically damped	α = ω₀	one repeated, −α	(A₁ + A₂t)e^−αt
Underdamped	α < ω₀	−α ± jω_d, ω_d = √(ω₀² − α²)	e^−αt(B₁ cos ω_dt + B₂ sin ω_dt)

Complete response = forced + natural. The forced part for a DC source is simply the t → ∞ value from the snapshot. Write x(t) = x(∞) + (natural form) first, and then fit the two constants to x(0⁺) and dx/dt(0⁺). Two unknown constants need two conditions, which is why section 4's derivative work is compulsory here.

The routine: (1) 0⁻ values; (2) α, ω₀ → case → roots; (3) forced value x(∞); (4) x(0⁺) and dx/dt(0⁺) from the element laws; (5) solve for the constants.

Same L = 1 H, C = 0.25 F (so ω₀ = 2 rad/s), capacitor starting at 1 V, three values of R. Only α changes.

Worked example 6Series RLC, overdamped

Worked example 6. One loop, so one current i; it leaves the capacitor's + plate.

The inductor carries no current before the switch closes. Find i(t) for t ≥ 0.

Classify: α = R/2L = 10/2 = 5 s⁻¹; ω₀ = 1/√(1 × 1/16) = 4 rad/s. α > ω₀, so the circuit is overdamped.
Roots: s = −5 ± √(25 − 16) = −5 ± 3, giving s₁ = −2, s₂ = −8. Check: the equation is s² + 10s + 16 = (s + 2)(s + 8) ✓.
Forced: the capacitor blocks DC, so i(∞) = 0 and i(t) = A₁e^−2t + A₂e^−8t.
Initial values: i(0⁺) = 0 (inductor). KVL around the loop at 0⁺: v_C = Ri + L di/dt, so 12 = 0 + 1 · di/dt, giving di/dt(0⁺) = 12 A/s.
Constants: A₁ + A₂ = 0 and −2A₁ − 8A₂ = 12. Substitute A₂ = −A₁: 6A₁ = 12. So i(t) = 2(e^−2t − e^−8t) A.
Extras: the peak is where di/dt = 0: −4e^−2t + 16e^−8t = 0, so e^6t = 4 and t = ln 4/6 = 0.231 s, where i = 0.945 A. The capacitor voltage is v_C = Ri + L di/dt = 16e^−2t − 4e^−8t V; at t = 0 that gives 12 V ✓.

Worked example 6, computed: overdamped — up once, down once, never crosses zero.

Worked example 7Series RLC, underdamped (and the radians trap)

Worked example 7. One loop, so one current i; it leaves the capacitor's + plate.

Same set-up as example 6, with different values. Find i(t) and i(0.5 s).

Classify: α = 2/2 = 1 s⁻¹; ω₀ = 1/√0.2 = √5 ≈ 2.236 rad/s. α < ω₀, so the circuit is underdamped, with ω_d = √(5 − 1) = 2 rad/s.
Form: the forced value is 0 again, so i(t) = e^−t(B₁ cos 2t + B₂ sin 2t).
First condition: i(0⁺) = 0. Since cos 0 = 1 and sin 0 = 0, this gives B₁ = 0.
Second condition: by the same KVL as example 6, di/dt(0⁺) = v_C(0⁺)/L = 10 A/s. The derivative of B₂e^−t sin 2t at 0 is 2B₂, so B₂ = 5.
Unpack: the product rule at t = 0

d/dt[e^−t sin 2t] = −e^−t sin 2t + e^−t · 2 cos 2t. At t = 0 that is −1·0 + 1·2·1 = 2. See the kit.
Answer: i(t) = 5e^−t sin 2t A. At 0.5 s: 5 × e^−0.5 × sin(1 rad) = 5 × 0.6065 × 0.8415 = 2.55 A. With the calculator in degree mode, sin(1°) gives 0.053 A, fifty times too small.
Bonus: v_C = Ri + L di/dt = e^−t(10 cos 2t + 5 sin 2t) V; at t = 0 that gives 10 V ✓.

Worked example 7, computed: underdamped — a sine wave squeezed by the dashed e^−αt envelope. Period 2π/ω_d = π ≈ 3.14 s.

Worked example 8Parallel RLC, critically damped, with a forced response

Worked example 8. Four elements, two nodes: everything shares the one voltage v. The source steps from 0.5 A to 2 A at t = 0.

The source current is i_s = 0.5 A for t < 0 (for a long time) and 2 A for t > 0. Find i_L(t) and v(t).

0⁻: the inductor is a short across everything, so v(0⁻) = 0, and all the source current goes through it: i_L(0⁻) = 0.5 A.
Classify: parallel, so α = 1/(2RC) = 1/(2 × 1.25 × 0.04) = 10 s⁻¹. ω₀ = 1/√(0.25 × 0.04) = 1/√0.01 = 10 rad/s. α = ω₀, so the circuit is critically damped, with double root s = −10.
Forced: at ∞ the inductor shorts again, so i_L(∞) = 2 A. Form: i_L(t) = 2 + (A₁ + A₂t)e^−10t.
First condition: i_L(0⁺) = 0.5, so 2 + A₁ = 0.5 and A₁ = −1.5.
Second condition: di_L/dt(0⁺) = v(0⁺)/L = 0, because the capacitor voltage is continuous. Differentiating the form at 0 gives −10A₁ + A₂ = 0, so A₂ = −15.
Answer: i_L(t) = 2 − (1.5 + 15t)e^−10t A. Then v = L di_L/dt = 0.25 × [−15 + 10(1.5 + 15t)]e^−10t = 37.5t e^−10t V, which peaks at 1.38 V at t = 0.1 s.

If you drop the forced "2 +" in step 3, the fit gives a current decaying to 0 A, even though the source keeps pushing 2 A forever. A final value that disagrees with the ∞ snapshot is always a warning sign.

Worked example 8, computed: critically damped — starts flat (because v(0⁺) = 0), then climbs to the forced value 2 A without overshooting.

Classic traps: the module's mark-losers

1) Carrying 0⁻ values of the wrong things. Only v_C and i_L carry over. In example 1 the 2 kΩ current went from 0 to 7 mA in an instant. Find every other 0⁺ value from the 0⁺ circuit. 2) Killing the dependent source when finding R_th. In example 2 that turns 1.6 Ω into 2.4 Ω and ruins τ. Use a test source, or V_oc/I_sc. 3) The sign of v_L in di/dt(0⁺). Write the KVL with node voltages as in example 5 (L di/dt = v_left − v_right for i flowing left → right) instead of guessing the sign. 4) Series vs parallel α. Series R/2L, parallel 1/2RC. Using the wrong one can flip the damping case. 5) Forgetting the forced term before fitting the constants (example 8). 6) Degrees mode for cos ω_dt and sin ω_dt. It must be radians (example 7). 7) Not restarting the clock at a second switching: e^{−(t−t₀)/τ} (example 3).

6 · Your minimal prerequisite kit

e^x and ln: e⁻¹ ≈ 0.368; e⁻⁵ < 1%. Solve e^−t/τ = k by taking ln of both sides: t = −τ ln k = τ ln(1/k).
The quadratic formula s = (−b ± √(b² − 4ac))/2a. The sign of the discriminant is exactly the over/critical/under test.
Differentiating e^st (gives se^st), plus the product rule for t e^−αt and e^−αt sin ω t. The MATH daily drill covers these.
∫₀^∞e^−ktdt = 1/k, for energy questions.
Calculator in radians for every transient. Set it before the exam starts.
Series/parallel reduction and Thevenin, from Module 2 §4. Every τ is an R_th in disguise.

7 · What to practise

Skill	Where	How many
First-order RC/RL with a switch (0⁻, 0⁺, ∞, τ)	Bobrow Ch. 3 problems on first-order circuits (within §3.2–3.5)	6–8, including two with a dependent source (test-source τ)
Two switching events; time to reach a value; energy in a resistor	Same sections	3–4
Initial conditions including dx/dt(0⁺), d²x/dt²(0⁺)	Ch. 3 second-order problems	3–4
Series and parallel RLC: all three cases, at least one with a DC forced term	Ch. 3 second-order problems	6: two of each case

The handout names §3.2–3.5 as one block. Check in your copy which subsections hold first-order and which hold second-order circuits. Whether this edition prints answers in the back is also unverified, so check that once too. The past mid-sem papers are the best practice set of all: they show exactly how these families are asked.